The field of the present invention is electronic circuits. More particularly, the present invention relates to an electronic configuration for use with a phase-locked loop circuit.
A phase-locked loop (PLL) circuit is widely used in electronics to synchronize or detect signal phase. In a specific application, PLL""s are used in frequency-synthesized radio transmitters and receivers, and may be used as a detector in a frequency-modulation or phase-modulation receiver. Often, the PLL is used to synchronize signal-processing circuitry with an input signal. For example, the processing circuitry in a wireless device is generally synchronized with a received signal to facilitate processing and decoding information in the input signal.
The known PLL circuit is generally configured to receive an input signal from an outside source. For example, the input signal may be a signal received at an antenna member for a wireless device. The conventional PLL also has a voltage-controlled oscillator (VCO) outputting a reference signal. The known PLL uses a phase detector circuit that compares the phase of the input signal to the reference signal, and adjusts the VCO with a tuning voltage. Over time, the output signal of the VCO is adjusted to be in-phase with the input signal.
The time it takes to synchronize the reference signal to the input signal is commonly referred to as the lock-time. Lock-time is typically measured in clock cycles, and can be, for example, one hundred or more clock cycles long. During lock-time, processing circuitry is not synchronized with the input signal and is therefore not able to accurately and consistently process the input signal. It is therefore desirable that lock-time be as short as possible.
However, lock-time is dependent on many factors, and therefore lock-time will vary depending on specific conditions. For example, the gain of both the phase detector and the VCO will vary due to changes in temperature or supply voltage. Also, the gain of the VCO typically varies depending on the tuning voltage applied. Indeed, the response of the VCO may be highly non-linear, with a high gain when receiving a low tuning voltage, and a much lower gain when receiving a higher tuning voltage. Such non-linearity may lead to substantial variations in VCO response. Accordingly, the lock-time can vary widely. Due to this lack of predictability and consistency in lock-time, the processing circuitry is often configured to accommodate the longest expected lock-time.
There is therefore a need for a PLL circuit having a short lock-time. It would also be desirable that the lock-time be consistent and predictable.
It is therefore an object of the present invention to provide a PLL circuit with a more predictable and consistent lock time. It is another separate object of the present invention to reduce lock-time. To overcome the deficiencies in the known art, and to meet the stated objectives, a method and circuit for improving lock-time performance is provided.
Briefly, the present invention provides gain control for a phase locked loop circuit. In the phase-locked loop circuit, a voltage-controlled oscillator generates a reference signal responsive to the level of a tuning voltage. A phase detector generates a change in, or update to, the tuning voltage, which is indicative of a phase relationship between the reference signal and an input signal. A feedback circuit detects the tuning voltage and generates an adjustment signal in response. The adjustment signal is then used to adjust the phase detector gain to compensate for the non-linear gain of the voltage-controlled oscillator. In a specific example, the adjustment signal is used to adjust the current gain of the phase detector in a manner that is complementary to the non-linear voltage gain of the voltage-controlled oscillator.
Advantageously, the method and circuit for improving lock-time performance compensates for the non-linearity of the voltage controlled oscillator. In such a manner, the product of the gains of the voltage-controlled oscillator and the phase detector remain fairly constant, so the response characteristics of the phase-locked loop are more predictable. Accordingly, the lock time for the PLL becomes more predictable and may be reduced.
These and other features and advantages of the present invention will be appreciated from review of the following detailed description of the invention, along with the accompanying figures in which like reference numerals refer to like parts throughout.